In memory circuits comprised of cells which are conducting current in a logic "0" state and are not conducting current in a logic "1" state, sense amplifiers are designed to sense current flow for a determination as to whether a logic "1" or a logic "0" is stored by an addressed memory cell. In a conventional memory circuit, the memory cells are arranged in an array established by rows and columns with one memory cell at each intersection of a row and column. A memory cell to be read is coupled to the sense amplifier by coupling the column which contains the memory cell to be read to the sense amplifier via a column decoder. Because such a column has a relatively large capacitance, current flows into the column for some duration even when the memory cell to be read is not conducting current. Consequently there is a delay time before a logic "1" can be detected.
To minimize this delay time, techniques have been developed to rapidly charge the column capacitance with a charging circuit. The charging circuit provides a relatively large amount of current until a first predetermined voltage on the column is reached. A second charge circuit continues to supply current unless a second predetermined voltage is reached at which time a current stops flowing implying the memory cell to be read is in a logic "1" state. If the memory cell to be read is in a logic "0" state, the memory cell conducts sufficient current so that the second charge circuit will not drive the column to the second predetermined voltage. In the prior art the two charge circuits comprise insulated gate field effect transistors of differing sizes. The difference in the two predetermined voltages is established by the difference in ratio of the size of certain transistors in the two charge circuits. Consequently the difference between the two predetermined voltages is dependent upon the ability of the process for manufacturing the transistors to control size ratios. Size ratios are typically easier to control than absolute sizes, but there is still some undesirable variation in size ratios. Consequently the design of the charge circuits must include a consideration of the variation in size ratio over process variations. The size ratios of the two charge circuits must be designed to be of sufficient difference to ensure that the first predetermined voltage is less than the second predetermined voltage over process variation. At the same time, however, it is desirable for the difference between the two predetermined voltages to be minimized in order to minimize the time for the column voltage to traverse from the first to the second predetermined voltage in the case where the memory cell to be read is in a logic "1" state.